Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications

Nayana V S; Harshitha B; Madhusudhan K N

doi:10.5455/jeas.2025011207

Journal of Engineering and Applied Sciences. 2025; 12(2): 66-73

doi: 10.5455/jeas.2025011207

Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications

Nayana V S, Harshitha B, Madhusudhan K N.

Abstract
Power dissipation stands as a crucial challenge in VLSI design, especially for high-speed counters used in frequency synthesizers, PLLs, and digital converters. Conventional binary counters suffer from large fan-out and propagation delays, while traditional LFSR counters operate with only (2^m – 1) states, requiring additional circuitry for full counting sequences. This work proposes a novel LFSR counter with a state extension technique that achieves 2^m states without degrading the counting rate. The architecture combines a low-order LFSR sub-counter and a high-order synchronous binary counter, optimized with clock gating to reduce unnecessary switching activity. Implemented using Verilog HDL in Xilinx ISE/Vivado, the proposed design demonstrates significant improvements: power reduced from 249 mW to 114 mW (54% savings) while maintaining constant delay performance. Compared to conventional binary and LFSR counters, the design achieves superior trade-offs in power, speed, and area, making it highly suitable for advanced high-speed VLSI applications.

Key words: Arithmetic and Logic units; Clock gating, Combinational Logic; High speed Arithmetic; High Speed Counter; LFSR State Extension; Low Power Techniques; Sequential circuits.

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How to Cite this Article

Pubmed Style

S NV, B H, N MK. Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences. 2025; 12(2): 66-73. doi:10.5455/jeas.2025011207

Web Style

S NV, B H, N MK. Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. https://jecasmu.org/?mno=264060 [Access: December 29, 2025]. doi:10.5455/jeas.2025011207

AMA (American Medical Association) Style

S NV, B H, N MK. Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences. 2025; 12(2): 66-73. doi:10.5455/jeas.2025011207

Vancouver/ICMJE Style

S NV, B H, N MK. Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences. (2025), [cited December 29, 2025]; 12(2): 66-73. doi:10.5455/jeas.2025011207

Harvard Style

S, N. V., B, . H. & N, . M. K. (2025) Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences, 12 (2), 66-73. doi:10.5455/jeas.2025011207

Turabian Style

S, Nayana V, Harshitha B, and Madhusudhan K N. 2025. Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences, 12 (2), 66-73. doi:10.5455/jeas.2025011207

Chicago Style

S, Nayana V, Harshitha B, and Madhusudhan K N. "Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications." Journal of Engineering and Applied Sciences 12 (2025), 66-73. doi:10.5455/jeas.2025011207

MLA (The Modern Language Association) Style

S, Nayana V, Harshitha B, and Madhusudhan K N. "Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications." Journal of Engineering and Applied Sciences 12.2 (2025), 66-73. Print. doi:10.5455/jeas.2025011207

APA (American Psychological Association) Style

S, N. V., B, . H. & N, . M. K. (2025) Maximizing Digital Counting Efficiency With LFSR State Extension For High-Speed Applications. Journal of Engineering and Applied Sciences, 12 (2), 66-73. doi:10.5455/jeas.2025011207